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r01ds0240ej0111 rev.1.11 page 1 of 13 feb 18, 2015 datasheet sh74582 renesas mcu 1. overview the sh7458 group is a single-chip risc (reduced instruction set computer) microcontroller based on a renesas original risc cpu core. basically the sh7458 group is the same as the sh7456 group. please refer to sh7455 group, sh7456 group user?s manual: hardware rev.1.10 (sep 22, 2011). table 1.1 shows the differences between the sh7456 group and the sh7458 group. * henceforth, the bold letter portion (shaped portion) shows a difference from sh7456 group. table 1.1 products group product model cpu frequency memory capacity package flexray operating temperature (ta) sh7458 sh74582 r5f74582kbg 160mhz rom: 1mbytes il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 512 kbytes prbg0176ga-a yes -40 to +125c sh7455 sh74552 r5f74552kbg 160mhz rom: 1mbyte il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 256 kbytes prbg0176ga-a yes -40 to +125c sh7456 sh74562 r5f74562kbg 160mhz prbg0176ga-a no -40 to +125c sh7457 sh74572 r5f74572lbg 240mhz rom: 1mbyte il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 256 kbytes prbg0176ga-a yes -40 to +105c sh7459 sh74593 r5f74593lbg 240mhz rom: 1.5mbytes il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 512 kbytes prbg0176ga-a yes -40 to +105c 2. details this section shows the details of the difference from sh7455 group, sh7456 group user?s manual: hardware rev.1.10 (sep 22, 2011). table 2.1 shows the difference between the sh74562 and the sh74582. table 2.1 difference between sh74562 and sh74582 page description 1-1 ? 1.1 features product superhyway ram (shwyram) capacity sh74562 256 kbytes sh74582 512 kbytes 1-4 ? table 1.1 specifications overview: descriptions of ram product ram capacity sh74562 256-kbyte sh74582 512 -kbyte r01ds0240ej0111 rev.1.11 feb 18, 2015
sh74582 2. details r01ds0240ej0111 rev.1.11 page 2 of 13 feb 18, 2015 page description 1-6 ? table 1.1 specifications overview: descriptions of flexray product channels of flexray sh74562 none: sh7456 group sh74582 two channels : sh7458 group 1-7 ? table 1.2 products product model shwyram capacity flexray sh74562 r5f74562kbg 256 kbytes no sh74582 r5f74582kbg 512 kbytes yes please refer to appendix a. 1-8 ? figure 1.1 block diagram product shwyram capacity sh74562 shwyram (256 kbytes) sh74582 shwyram ( 512 kbytes) 11-2 ? figure 11.2 address space (p0/u0 area): description s of 29-bit physical address space (single chip) product shwyram capacity (start address ? last address) sh74562 256 kbytes (h ?1800 0000 ? h?1803 ffff) sh74582 512 kbytes (h?1800 0000 ? h?1807 ffff ) please refer to appendix b.1. 11-3 ? figure 11.3 address space (p1 area): descriptions of 29-bit physical address space (single chip) product shwyram capacity (start address ? last address) sh74562 256 kbytes (h ?9800 0000 ? h?9803 ffff) sh74582 512 kbytes (h?9800 0000 ? h?9807 ffff ) please refer to appendix b.2. 11-4 ? figure 11.4 address space (p2 area): descriptions of 29-bit physical address space (single chip) product shwyram capacity (start address ? last address) sh74562 256 kbytes (h ?b800 0000 ? h?b803 ffff) sh74582 512 kbytes (h?b800 0000 ? h?b807 ffff ) please refer to appendix b.3. 11-5 ? figure 11.5 address space (p3 area): descriptions of 29-bit physical address space (single chip) product shwyram capacity (start address ? last address) sh74562 256 kbytes (h ?d800 0000 ? h?d803 ffff) sh74582 512 kbytes (h?d800 0000 ? h?d807 ffff ) please refer to appendix b.4. 13-1 ? 13.1 overview product page structure sh74562 64-kbyte units (pages 0 to 3) sh74582 64-kbyte units (pages 0 to 7 ) ? figure 13.1 block diagram of shwyram : descriptions of memory block product page number [capacity] sh74562 page 3 [64 kb] sh74582 page 7 [64 kb]
sh74582 2. details r01ds0240ej0111 rev.1.11 page 3 of 13 feb 18, 2015 page description 13-1 13-2 ? 13.1 overview product shwyram allocation sh74562 the upper 25 6 kbytes of area 6 (h'1800 0000 to h'1803 ffff in the 29-bit physical address space) sh74582 the upper 512 kbytes of area 6 (h'1800 0000 to h'1807 ffff in the 29-bit physical address space) ? figure 13.2 address space : descriptions of 29-bit physical address space (area 6) product shwyram capacity (start address ? last address) sh74562 256 kbytes (h ?1800 0000 ? h?1803 ffff) sh74582 512 kbytes (h?1800 0000 ? h?1807 ffff ) added the following pages page address (29-bit physical address) page 4 h?1804 0000 ? h?1804 ffff page 5 h?1805 0000 ? h?1805 ffff page 6 h?1806 0000 ? h?1806 ffff page 7 h?1807 0000 ? h?1807 ffff please refer to appendix c. 28-1 ? table 28.1 drii overview product access areas sh74562 all shwyram areas (up to 256 kbytes) sh74582 all shwyram areas (up to 512 kbytes) please refer to appendix d.1. 28-46 ? 28.3.23 drii address reload registers 0 and 1 ( driiadr0rld and driiadr1rld) : description of driadmrld bit product description sh74562 address bits 18 to 2 reload value (256-kbyte area) sh74582 address bits 18 to 2 reload value ( 512 -kbyte area) please refer to appendix d.2. 28-47 ? 28.3.24 drii address counters 0 and 1 (driiadr0 ct and driiadr1ct) : description of driadn bit product description sh74562 destination address bits 18 to 2 (256-kbyte area) sh74582 destination address bits 18 to 2 ( 512 -kbyte area) please refer to appendix d.3. 29-1 ? table 29.1 dro module overview product access area sh74562 shwyram area (256 kbytes) sh74582 shwyram area ( 512 kbytes) please refer to appendix e.
sh74582 appendix a r01ds0240ej0111 rev.1.11 page 4 of 13 feb 18, 2015 appendix a section 1 overview 1.2 product line overview table 1.2 lists the products. table 1.2 products product model rom capacity ram capacity package flexray sh74552 r5f74552kbg 1 mbyte il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 256 kbytes prbg0176ga-a yes sh74562 r5f74562kbg no sh74572 r5f74572lbg yes sh74582 r5f74582kbg il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 512 kbytes yes sh74593 r5f74593lbg 1.5 mbytes il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 512 kbytes yes
sh74582 appendix b r01ds0240ej0111 rev.1.11 page 5 of 13 feb 18, 2015 appendix b appendix b.1 section 11 address space for details on the p0/u0 area to the p4 area, see figures 11.2 to 11.6. area 1 area 2 area 3 area 4 area 5 32-bit virtual address space via cpu 29-bit physical address space single chip internal rom (1 mbyte) reserved reserved reserved reserved note: the cpu, dmac, audr, and other modules cannot access a reserved area. but the cpu can access area 7 as a control register area using the mmu. h'03ff ffff h?0400 0000 h'07ff ffff h?0800 0000 h'0bff ffff h?0c00 0000 h'0fff ffff h?1000 0000 h'13ff ffff h?1400 0000 h'17ff ffff h?1800 0000 h'1bff ffff h?1c00 0000 h'1fff ffff h?0000 0000 h'1807 ffff h?1808 0000 p0/u0 area (512 mbytes) area 0 area 6 area 7 shwyram (512kbytes) h'000f ffff h?0010 0000 figure 11.2 address space (p0/u0 area)
sh74582 appendix b r01ds0240ej0111 rev.1.11 page 6 of 13 feb 18, 2015 appendix b.2 section 11 address space area 1 area 2 area 3 area 4 area 5 32-bit virtual address space via cpu 29-bit physical address space single chip internal rom (1 mbyte) reserved reserved reserved reserved note: the cpu, dmac, audr, and other modules cannot access a reserved area. h'83ff ffff h?8400 0000 h'87ff ffff h?8800 0000 h'8bff ffff h?8c00 0000 h'8fff ffff h?9000 0000 h'93ff ffff h?9400 0000 h'97ff ffff h?9800 0000 h'9bff ffff h?9c00 0000 h'9fff ffff h?8000 0000 h'9807 ffff h?9808 0000 p1 area (512 mbytes) area 0 area 6 area 7 shwyram (512kbytes) h'800f ffff h?8010 0000 figure 11.3 address space (p1 area)
sh74582 appendix b r01ds0240ej0111 rev.1.11 page 7 of 13 feb 18, 2015 appendix b.3 section 11 address space area 1 area 2 area 3 area 4 area 5 32-bit virtual address space via cpu 29-bit physical address space single chip internal rom (1 mbyte) reserved reserved reserved reserved note: the cpu, dmac, audr, and other modules cannot access a reserved area. h'a3ff ffff h?a400 0000 h'a7ff ffff h?a800 0000 h'abff ffff h?ac00 0000 h'afff ffff h?b000 0000 h'b3ff ffff h?b400 0000 h'b7ff ffff h?b800 0000 h'bbff ffff h?bc00 0000 h'bfff ffff h?a000 0000 h'b807 ffff h?b808 0000 p2 area (512 mbytes) area 0 area 6 area 7 shwyram (512kbytes) h'a00f ffff h?a010 0000 figure 11.4 address space (p2 area)
sh74582 appendix b r01ds0240ej0111 rev.1.11 page 8 of 13 feb 18, 2015 appendix b.4 section 11 address space area 1 area 2 area 3 area 4 area 5 32-bit virtual address space via cpu 29-bit physical address space single chip internal rom (1 mbyte) reserved reserved reserved reserved note: the cpu, dmac, audr, and other modules cannot access a reserved area. but the cpu can access area 7 as a control register area using the mmu. h'c3ff ffff h?c400 0000 h'c7ff ffff h?c800 0000 h'cbff ffff h?cc00 0000 h'cfff ffff h?d000 0000 h'd3ff ffff h?d400 0000 h'd7ff ffff h?d800 0000 h'dbff ffff h?dc00 0000 h'dfff ffff h?c000 0000 h'd807 ffff h?d808 0000 p3 area (512 mbytes) area 0 area 6 area 7 shwyram (512kbytes) h'c00f ffff h?c010 0000 figure 11.5 address space (p3 area)
sh74582 appendix c r01ds0240ej0111 rev.1.11 page 9 of 13 feb 18, 2015 appendix c section 13 superhyway ram (shwyram) 13.1 overview as shown in figure 13.2, the shwyram is allocated to the upper 512 kbytes of area 6 (h'1800 0000 to h'1807 ffff in the 29-bit physi cal address space). address (29-bit physical address) h'1800 0000 to h'1800 ffff h'1801 0000 to h'1801 ffff h'1802 0000 to h'1802 ffff h'1803 0000 to h'1803 ffff h'1804 0000 to h'1804 ffff h'1805 0000 to h'1805 ffff h'1806 0000 to h'1806 ffff h'1807 0000 to h'1807 ffff page page 0 page 1 page 2 page 3 page 4 page 5 page 6 page 7 area 6 of p0/u0 area (64 mb) h'1800 0000 h'1800 0000 h'1807 ffff h'1808 0000 h'1bff ffff 32-bit virtual address space reserved (access not allowed) shwyram (512kb) h'1bff ffff area 6 of p1 area (64 mb) area 6 of p2 area (64 mb) area 6 of p3 area (64 mb) h'9800 0000 h'9bff ffff h'b800 0000 h'bbff ffff h'd800 0000 h'dbff ffff 29-bit physical address space (area 6) figure 13.2 address space
sh74582 appendix d r01ds0240ej0111 rev.1.11 page 10 of 13 feb 18, 2015 appendix d section 28 direct ram input interface (dri) appendix d.1 28.1 overview table 28.1 lists the overview of the drii modules. table 28.1 drii overview item description number of channels 3 channels operating frequency 80 mhz (when pack = 80 mhz) transfer method clock synchronous parallel input access areas all shwyram areas (up to 512 kbytes) maximum transfer rate 80 mbytes/second (wh en the drii operating frequency is 80 mhz) minimum data acquisition period the following are the minimum periods when the drii operating frequency is 80 mhz. 43.75 ns (special mode disabled and the input data bus width is 8 or 16 bits) 25 ns (special mode enabled) data acquisition bus width 8 or 16 bits event counter 16 bits ? 6 counters (dec5 to dec0) bank switching function two banks can be specif ied as the data storage destination in shwyram data acquisition edges either rising edges , falling edges, or both edges can be selected acquisition timing adjustment function sets the time between detection of the data acquisition edge and the acquisition operation decimation control function data can be acquired se lectively using an event counter (dec5 to dec0)
sh74582 appendix d r01ds0240ej0111 rev.1.11 page 11 of 13 feb 18, 2015 appendix d.2 28.3.23 drii address reload registers 0 and 1 (driiadr0rld and driiadr1rld) driiadr0ct and driiadr1ct are registers that hold counter reload values. when reload mode is selected with the drii transfer control register (driitrmcnt) admd (a ddress counter operating mode selection) bit, the corresponding drii address counters are reloaded with the values set in these registers when the drii data acquisition control register (driidcapcnt) dcpen (acquis ition enable) bit changes from "0" to "1". note: ? these registers may only be rewritten when the drii data acquisition control register (driidcapcnt) dcpen (acquisition enable) bit is in the "0" state. dri0 address reload register 0 (dri0adr0rld) dri1 address reload register 0 (dri1adr0rld) dri2 address reload register 0 (dri2adr0rld) bit: bit: after reset: after reset: ???????????? ? ?? driad0rld 00000000000000 0 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 876543210 driad0rld 31 16 00000000000000 0 0 dri0 address reload register 1 (dri0adr1rld) dri1 address reload register 1 (dri1adr1rld) dri2 address reload register 1 (dri2adr1rld) bit: bit: after reset: after reset: ???????????? ? ?? driad1rld 00000000000000 0 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 876543210 driad1rld 31 16 00000000000000 0 0 bit abbreviation after reset r w description 31 to 19 ? all 0 0 0 reserved bits these bits are always read as "0". the write value should always be "0". 18 to 2 driadmrld all 0 r w address bits 18 to 2 reload value ( 512 -kbyte area) 1, 0 ? all 0 0 0 reserved bits these bits are always read as "0". the write value should always be "0". legend: m = 0 or 1
sh74582 appendix d r01ds0240ej0111 rev.1.11 page 12 of 13 feb 18, 2015 appendix d.3 28.3.24 drii address counters 0 and 1 (driiadr0ct and driiadr1ct) the driiadr0ct and driiadr1ct counters are provided to specify bits a18 to a2 of the address in shwyram that is the drii module transfer destin ation. bits a31 to a19 are fixed at "0 ". these counters are incremented by "4" each time a drii transfer completes. there are two drii ad dress counter operating modes, and applications can select the mode with the drii transfer control register (dri itrmcnt) admd bit. see the documentation of the drii transfer control register (driitrmcnt) for details. notes: ? if a drii address counter value is a value other than an area in which shwyram is located, the drii module will behave as though the drii transfers comp lete, but no writes of the acquired data will be performed whatsoever. ? a drii address counter is incremented by "4" when a drii transfer completed. this is performed for the one that is active at that time according to the setting of the drii transfer cont rol register (driitrmcnt) adsl (address counter selection) bit. ? these registers must only be rewritten in the state where a drii transfer coun ter (driitrmct) underflow has occurred (the counter is stopped at the value h'0000 0000). dri0 address counters 0 (dri0adr0ct) dri1 address counters 0 (dri1adr0ct) dri2 address counters 0 (dri2adr0ct) bit: bit: after reset: after reset: ???????????? ? ?? driad0 00000000000000 0 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 876543210 driad0 31 16 00000000000000 0 0 dri0 address counters 1 (dri0adr1ct) dri1 address counters 1 (dri1adr1ct) dri2 address counters 1 (dri2adr1ct) bit: bit: after reset: after reset: ???????????? ? ?? driad1 00000000000000 0 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 876543210 driad1 31 16 00000000000000 0 0 bit abbreviation after reset r w description 31 to 19 ? all 0 0 0 reserved bits these bits are always read as "0". the write value should always be "0". 18 to 2 driadn all 0 r w destination address bits 18 to 2 ( 512 -kbyte area) 1, 0 ? all 0 0 0 reserved bits these bits are always read as "0". the write value should always be "0". legend: n = 0 or 1
sh74582 appendix e r01ds0240ej0111 rev.1.11 page 13 of 13 feb 18, 2015 appendix e section 29 direct ram ou tput interface (dro) 29.1 overview table 29.1 lists the overview of the dro module. table 29.1 dro module overview item description transfer method parallel strobed output access area shwyram area ( 512 kbytes) output data width either 8-bits or 16-bits maximum transfer clock 10 mhz maximum transfer rate 20 mbytes/s (when 16 bits is selected, pck = 40mhz) strobe polarity either "h" active or "l" active may be selected. timing adjustment function the setup and hold times can be programmed in 1pck units relative to the strobe signal edge. interrupt request an interrupt request is generated afte r a prespecified number of data items have been output.
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history sh74582 datasheet rev. date description page summary 1.10 oct 20, 2014 - first edition issued 1.11 feb 18, 2015 1 corrected shwyram capacity of r5f74572lbg. (error) 512k -> (correct) 256k

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